By Ken Butti
Sm 4to, 1980, PP.289,
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Extra info for A Golden Thread: 2500 Years of Solar Architecture and Technology
2 ! 3 ! 4 - 5 6 A0-A15 K FFFC X fFFII X FFFF FFFE FFFD FFFC FFFB FFFA program ' starting address Fig. —«^ microprocessor. The microprocessor completes the current instruction being executed before recognizing this request (the IRQ input is sampled during Φ2 and the interrupt sequence starts on the next Φ1). e. I = 0), the microprocessor begins its interrupt sequence, which consists of the following steps: (i) (ii) the program counter and status register contents are stored on the stack; the interrupt mask flag is set (I = 1) to prevent the microprocessor from responding to further interrupt requests during this sequence; (iii) addresses FFFE 16 and FFFF 1 6 are generated, in sequence, by the microprocessor, and the IRQ vector is fetched from these locations; and (iv) the program counter is loaded with the IRQ vector, and control is handed over to the interrupt service routine (ISR) whose starting address is defined by the contents of memory locations FFFE 1 6 and F F F F 1 6 .
42 may be connected to form a 1K x S bit RAM* Two 1 K x 4 bit RAMs of the type shown in Fig. 42 may be connected to form a 1 K x 8 bit RAM as shown in Fig. 43. ProbtemtU Show how a 2 K x 8 bit EPROM and two 1 K x 8 hit RAMs of the type shown in F%. 44 may be connected to form a contiguous 4 K block of mmi0ty9 with the BFROM occupying the lower 2 & blocie of addresses. It is necessary in this circuit to decode the addresses into 1 K blocks to allow the selection of each of the individual RAM chips to take place.
A problem then occurs due to the fact that the EPROM must respond to a 2 K block of addresses. This problem is dealt with by decoding A 1 0 and A n to give four chip enable signals, each capable of selecting a 1 K block of memory, and to use two of these signals, suitably combined, to select the EPROM. An AND gate may be used for this purpose, as shown in Fig. 45. If either Y 0 or Y t is at a logical 0, the output from the AND gate is also at a logical 0 and the EPROM is selected, thus placing the EPROM in the lower 2 K addresses of the 4 K memory block.
A Golden Thread: 2500 Years of Solar Architecture and Technology by Ken Butti