New PDF release: A Designer s Guide to Built-in Self-Test

By Charles E. Stroud

ISBN-10: 1402070500

ISBN-13: 9781402070501

A contemporary technological improve is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). This inspiration was once first proposed round 1980 and has grown to turn into one of many most vital trying out thoughts on the present time, in addition to for the long run. This e-book is written from a designer's point of view and describes the main BIST techniques which have been proposed and applied considering 1980, besides their benefits and barriers. The BIST methods comprise the integrated good judgment Block Observer, pseudo-exhaustive BIST concepts, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection recommendations for online trying out. specific consciousness is paid to system-level use of BIST to be able to maximize some great benefits of BIST via decreased trying out time and value in addition to excessive diagnostic answer. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 construction VLSI units and three construction circuit forums. 16 of the VLSI units contained BIST of assorted kinds for normal buildings and normal sequential common sense, together with the first BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the prior 10 years in academia the place his learn and improvement maintains to target BIST, together with the first BIST for FPGAs and CPLDs in addition to endured paintings within the zone of BIST for common sequential good judgment and mixed-signal platforms. He holds 10 US patents (with five extra pending) for numerous sorts of BIST methods. as a result, the writer brings a special combination of data and event to this functional advisor for designers, attempt engineers, product engineers, procedure diagnosticians, and executives.

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Extra resources for A Designer s Guide to Built-in Self-Test

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One drawback of statistical fault sampling is that we loose the ability to target areas of the circuit for further design verification or further test vector development based on the undetected fault list since it is not a complete set of undetected faults. Otherwise, fault sampling provides an excellent method of reducing fault simulation time for very large circuits with minimal loss of accuracy in fault coverage determination. 1). However, there are other factors that influence the fault coverage calculation.

Since an open in a wire prevents the propagation of a signal past the open, inputs to gates and transistors on the other side of the open will remain constant, creating behavior equivalent to the gate-level and transistor-level fault models. As a result, opens can be detected by test vectors for either gate-level or transistor-level fault models. Therefore, only shorts between wires are of interest and they are more commonly referred to as bridging faults. 5a denoted A and B at the signal source end of the wires and A´ and B´ at the signal destination end of the wires with a resistive short between the two wires.

The second requirement of a good fault model, and just as important as the first, is that it must be computationally efficient with respect to the fault simulation environment. As we will see, these two requirements are often in opposition to each other. Currently, the most widely used fault models include gate-level faults, transistor-level faults, bridging faults, and delay faults. All of these fault models can be emulated in a simulation environment and, for the most part, they closely approximate the behavior of actual defects and faults that can occur during the manufacturing process and system operation.

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A Designer s Guide to Built-in Self-Test by Charles E. Stroud

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